1. Field of the Invention
The present invention generally relates to ring oscillator circuits formed on semiconductor substrates and, more particularly, to a ring oscillator circuit which is not easily affected by change of ambient temperature.
2. Description of the Background Art
Generally, an oscillator circuit for generating a reference clock signal is widely used to implement various electric circuits. In particular, a crystal oscillator circuit including a crystal vibrator has been frequently used since it can generate a clock signal having an extremely stable and constant frequency. However, the crystal oscillator circuit cannot be formed on a semiconductor substrate, so that it is connected to a semiconductor integrated circuit device to a printed circuit board. This increases the number of parts needed to constitute a circuit and also increases time consumed for work of mounting the parts. In addition, it is also pointed out that a crystal vibrator is generally expensive. Therefore, it has been desired to provide a cheaper oscillator circuit having a stable and constant oscillation frequency on a semiconductor substrate, that is to say, to form an on-chip oscillator. However, an oscillation frequency of the on-chip oscillator is generally unstable, and in particular, influence of change of ambient temperature cannot be avoided. Hence, in spite of increase in the number of parts and time for work of mounting the parts, a crystal oscillation circuit is mounted on a printed circuit board, so that the circuit is connected to a semiconductor integrated circuit device through the board.
Although the present invention is generally applicable to a semiconductor integrated circuit device which needs a clock signal having a stable oscillation frequency, a case in which the present invention is applied to interface LSI in an Integrated Services Digital Network (ISDN) as one example of a semiconductor integrated circuit device will be described below.
FIG. 10 is a block diagram of an interface LSI for an ISDN. Referring to FIG. 10, the interface LSI 1 comprises a receiver 2 receiving a received data signal DR, a frame converter 4 performing frame conversion of the received data and transmitted data, a driver 5 outputting a transmitted data signal DT. Frame converter 4 is connected to an upper circuit (not shown) in an ISDN.
Digital phase locked loop (hereinafter referred to as "DPLL") 3 receives the received data signal DR through receiver 2. A reference clock signal .phi.0 generated from an externally provided crystal oscillator (not shown) is applied to DPLL 3. DPLL 3 is responsive to the clock signal .phi.0 and outputs a clock signal .phi.2 synchronized with the received data signal DR. The clock signal .phi.2 is applied to frame converter 4 and a controller 6. Frame converter 4 performs conversion of sequence of data and data transfer speed in response to applied clock signal .phi.2. Controller 6 generates various clock signals necessary to control an internal circuit of the interface LSI 1 in response to clock signal .phi.2. If the frequency of the clock signal .phi.0 is changed for some reason, DPLL 3 gets to have an offset value. As a result, the pull-in range of DPLL 3 becomes narrow. It is pointed out that a clock signal having stable frequency should be applied as the clock signal .phi.0. The reference numeral 1 also denotes a semiconductor substrate, on which the whole circuit for the interface LSI is formed. A crystal oscillator generating reference clock signal .phi.0 is provided separately from interface LSI 1 and connected to interface LSI 1 through a printed circuit board not shown.
FIG. 11 is a block diagram of DPLL 3 shown in FIG. 10. Referring to FIG. 11, DPLL 3 comprises a phase detector 31 detecting an error between a phase of clock signal .phi.1 and a phase of clock signal .phi.2, a digital filter 32 receiving an error signal ER provided from phase detector 31, a controllable frequency divider 33 in which its ratio of frequency division can be controlled in response to a frequency-division-ratio controlling signal RC provided from digital filter 32.
In operation, controllable frequency divider 33 receives reference clock signal .phi.0 and provides clock signal .phi.2 whose frequency is controlled in response to frequency-division-ratio controlling signal RC. Phase detector 31 detects a phase difference between clock signals .phi.1 and .phi.2, and applies error signal ER indicating the phase difference to digital filter 32. Digital filter 32 removes extremely small signal components included in error signal ER and applies frequency-division-ratio controlling signal RC based on error signal ER to controllable frequency divider 33. A ratio of frequency division of controllable frequency divider 33 is controlled in response to frequency-division-ratio controlling signal RC. Controllable frequency divider 33 outputs clock signal .phi.2 having a renewed frequency.
Since interface LSI 1 shown in FIG. 10 does not comprise a reference clock signal generating circuit for generating reference clock signal .phi.0, inconveniences arising from increase in the number of parts and time consumed for work of mounting the parts are caused as mentioned before. To avoid these inconveniences, an interface LSI comprising a reference clock signal generator is desired.
FIG. 12 is a block diagram of an interface LSI 1' comprising a reference clock signal generator. Referring to FIG. 12, interface LSI 1' additionally comprises an internal clock signal generator 7 generating reference clock signal .phi.0, compared with interface LSI 1 shown in FIG. 10. Internal clock signal generator 7 is formed within a semiconductor substrate together with other circuits to constitute interface LSI 1'. As clock signal generator 7 which can be formed within a semiconductor substrate, a ring oscillator comprising an odd number of inverters cascaded in a ring-like manner is frequently used. However, the oscillation frequency of the ring oscillator is not stable, and in particular, it is easily affected by change of ambient temperature. The oscillation frequency of the ring oscillator varies with ambient temperature. This brings about an undesirable result in such a circuit which needs a stable reference clock signal as shown in FIG. 12. Therefore, it is necessary to form a ring oscillator circuit in a semiconductor substrate which is not easily affected by change of ambient temperature.
FIG. 13 is a circuit diagram of a conventional improved ring oscillator. The ring oscillator shown in FIG. 13 is disclosed in Japanese Patent Laying-Open No. 57-97218. Referring to FIG. 13, the ring oscillator comprises inverters 201 through 205 cascaded in a ring-like manner, RC circuit 401 through 405 positioned between respective ones of inverters 201 through 205, and a constant voltage source 107. Each of RC circuits determines a time period necessary to charge and discharge an input of an inverter succeeding the circuit. The oscillation frequency of the ring oscillator is determined depending on a time constant of RC circuits 401 through 405.
As a resistor provided within each of RC circuits 401 through 405, a diffused resistor formed in a semiconductor substrate is used. A diffused resistor and an on-resistor of a MOS transistor generally have a positive temperature coefficient. These resistance values increase as ambient temperature becomes high. Therefore, the oscillation frequency of the ring oscillator decreases as ambient temperature becomes high. That is to say, the oscillation frequency of the ring oscillator has a negative temperature coefficient. However, the ring oscillator shown in FIG. 13 comprises RC circuit 404 including a resistor 301 having a negative temperature coefficient, so that influence of change of ambient temperature on the oscillation frequency can be mitigated. As resistor 301 having a negative temperature coefficient, a polysilicon resistor is used.
However, the ring oscillator shown in FIG. 13 causes the following problem. Since RC circuits 401 through 405 for determining the oscillation frequency are connected in a ring of the cascaded inverters, a high oscillation frequency cannot be obtained. In order to obtain a high oscillation frequency, it is necessary to decrease a resistance value and a capacitance value of each of RC circuit 401 through 405; however these cannot be lowered so much as to prevent implementation of the aforestated temperature compensation. As a ring oscillator capable of generating a clock signal having a high oscillation frequency, a ring oscillator described below can be conceivable.
FIG. 2 is a circuit diagram of a ring oscillator showing the background of the present invention. Referring to FIG. 2, the ring oscillator 7a comprises 7 inverters 81 through 87 cascaded in a ring-like manner, PMOS transistors Q5 and Q6, NMOS transistors Q7 and Q8, a bias circuit constituted by an operational amplifier 72 and a resistor R1, and a constant voltage generating circuit 71. One inverter, for example, inverter 81 comprises PMOS transistors Q1, Q2 and NMOS transistors Q3, Q4 connected in series between a power supply potential V.sub.DD and a ground potential V.sub.SS. Transistors Q2 and Q3 have the gates connected to receive output signals from a preceding inverter (that is, inverter 87).
Operation of ring oscillator 7a shown in FIG. 2 will be described. A common connecting node N1 of transistor Q8 and resistor R1 is maintained at a constant voltage generated from constant voltage generating circuit 71 by operational amplifier 72 and transistor Q8. A current I1 determined by a resistance value of resistor R1 flows through resistor R1. Assume that a voltage at node N1 is VN1 and that a resistance value of resistor R1 is R1, and current Il can be shown by the following expression. EQU I1=VN1/R1 (1)
Assume that gate width and gate length of transistor Q5 are W5 and L5, respectively, that gate width and gate length of transistor Q6 are W6 and L6, respectively, and that the current mirror circuit has a ratio of current of 1:1, and the following expression can be obtained. EQU W5/L5=W6/L6 (2) EQU Therefore, EQU I1=I2 (3)
where I2 shows a current value of current flowing in transistor Q6.
Assume that gate widths and gate lengths of transistors Q1, Q4 and Q7 are W1 and L1; W4 and L4; W7 and L7, respectively, and an expression (6) can be obtained when the following expressions (4) and (5) are satisfied. EQU W1/L1=W6/L6 (4) EQU W4/L4=W7/L7 (5) EQU I3=I4=I2 (=I1) (6)
where currents I3 and I4 indicate current values of currents flowing through transistors Q1 and Q4, respectively.
Generally, the oscillation frequency of a ring oscillator increases as currents I3 and I4 become larger. That is, the oscillation frequency of a ring oscillator increases with increase of current supplied to an individual inverter. That is because, if current supplied to an individual inverter is increased, time needed to charge and discharge an input node of an succeeding inverter is decreased. On the other hand, if supply current is decreased, longer time to charge and discharge the input node of the succeeding inverter is necessary and the oscillation frequency becomes lower. Therefore, the oscillation frequency of the ring oscillator increases in proportion to supply currents I3 and I4 (additionally to I2 and I1).
As resistor R1 shown in FIG. 2, a diffused resistor formed in a semiconductor substrate is generally used. When, a p.sup.+ diffused resistor is used as a diffused resistor, for example, resistor R1 has a temperature characteristic shown in FIG. 3.
FIG. 3 is a graph showing a temperature characteristic of a p.sup.+ diffused resistor used as resistor R1. Referring to FIG. 3, ambient temperature is plotted on the abscissa and sheet resistivity (.OMEGA./.quadrature.) on the ordinate. As can be seen from FIG. 3, a resistance value of a diffused resistor increases as ambient temperature increases. In other words, a diffused resistor has a positive temperature coefficient. Therefore, when a diffused resistor is used as resistor R1 shown in FIG. 2, current I1 decreases as ambient temperature increases. In other words, current I1, additionally bias currents I2, I3 and I4 have negative temperature coefficients.
As a result, the oscillation frequency of a ring oscillator becomes gradually lower because of decrease of bias currents as temperature rises . The frequency of- a ring oscillator has a negative temperature coefficient based on a temperature characteristic of resistor R1.
It should be also pointed out, the oscillation frequency of a ring oscillator becomes gradually lower, as temperature rises based on a temperature characteristic of inverters cascaded in a ring-like manner. FIG. 4 is a characteristic chart showing a temperature characteristic of the oscillation frequency of an oscillation circuit constituted by inverters cascaded in a ring-like manner. Bias currents, namely current I3 and I4, are fixed in FIG. 4. Generally, on-resistance of an MOS transistor increases with a rise of ambient temperature. Therefore, even if bias currents are constant, current flowing through inverters constituting a ring oscillator decreases. As a result, as shown in FIG. 4, the oscillation frequency becomes lower as temperature rises. This means that the oscillation frequency of a ring oscillator becomes gradually lower, not only based on a temperature characteristic of resistor R1, but also based on a temperature characteristic of inverters. The oscillation frequency of a ring oscillator has a negative temperature coefficient based on the temperature characteristic of resistor R1 and the temperature characteristic of the inverters.
As already described, when a ring oscillator is used in a semiconductor integrated circuit device as a reference clock generating circuit, it is desirable to maintain an oscillation frequency constant. The oscillation frequency of the ring oscillator should not be affected by change of ambient temperature. However, the oscillation frequency of ring oscillator 7a shown in FIG. 2 becomes lower as temperature rises, as stated before. It is a problem when ring oscillator 7a shown in FIG. 2 is used.